(a) Field of the Invention
The present invention relates to a semiconductor large-scale integrated circuit (LSI) having a built-in self-test (BIST) circuit and, more particularly, to improvement of a BIST circuit installed in a LSI for testing the function of the logic circuit in the LSI.
(b) Description of the Related Art
IC tester is generally used In a test operation of a LSI. In a test operation of a high-speed LSI, the IC tester operates in a series of processing for the LSI, including transmitting a test pattern for operating the LSI, receiving resultant data from the LSI, comparing the resultant data against the expected data and judging pass/fail of the LSI. The series of the processing should be performed in accordance with the operational speed of the LSI under test, and thus the higher-speed LSI should be tested by the IC tester operating at a higher speed. However, since the higher-speed IC tester is expensive, it is desired to test the higher-speed LSI by using on ordinary IC tester operating at a lower speed and thus being less expensive.
It is usual that the high-speed LSI has a PLL circuit (PLL) for multiplying an external reference clock signal to generate an internal system clock signal for use within the LSI. In this case, the IC tester allows the higher-speed LSI to test itself by using the BIST circuit while operating the internal logic circuit with a higher-frequency system clock signal generated by the PLL. The BIST circuit receives the results of the self-test, stores compressed data for the test results, and transmits the test result data to the IC tester after the self-test is finished. This technique is described in Patent Publications JP-A-10-90362 and -11-30646, for example.
FIG. 1 shows signal flows between a conventional LSI and an IC tester during a self-test by the LSI. The LSI 20 includes a PLL circuit 13, a logic circuit 14 and a BIST circuit 15, and operates for self-test processing based on the test instruction supplied from the IC tester 12. The resultant data is transmitted from the BIST circuit 15 to the IC tester 12.
FIG. 2 shows a flowchart for the functional self-test conducted by the LSI 20 shown in FIG. 1. The IC tester 12 transmits a reference clock signal 101, and then a test enable signal 108 to the LSI 20. The LSI 20 starts for preparation of the functional self-test to generate the system clock signal after receiving the reference clock signal 101 at step S31, and starts for the functional self-test of the logic circuit 14 at step S32 after receiving the test enable signal 108. The BIST circuit 15 receives test result data 104 from the logic circuit 14, compresses the test result data 104, and stores the compressed data in step S33. After the functional self-test is finished by the BIST circuit 15, the LSI 20 transmits the test end signal 105 at step S34. The IC tester 12, after receiving the test end signal 105 from the LSI 20, transmits a data clock signal 106 to the LSI 20 in step S35. The LSI 20 transmits the test result data 107 in synchrony with the data clock signal 106 in step S36. The IC tester 12 then compares the test results in the test result data 107 against the expected data stored therein to judge pass/fail of the LSI.
There is a time interval (phase lock time) between the time instant at which the PLL circuit 13 starts for comparison of the phase between the reference clock signal and the system clock signal by using a feedback control and the time instant at which the phase lock is obtained after stabilization of the system clock signal. The IC tester 12 waits transmission of the test enable signal 108 to the LSI 20 during the phase lock time, which is different from LSI to LSI. The waiting time is set in the IC tester 12 in consideration of the general phase lock time in a variety of LSIs, especially adapting to a LSI having a long phase lock time.
Thus, in the test of the conventional LSI, the time interval between the steps S31 and S32 is too long for a high-performance LSI having a shorter phase lock time, and the IC tester waits for a longer time before transmission of the test enable signal to thereby lower the throughput of the functional self-test.
In view of the above, it is an object of the present invention to provide a LSI, which is capable of reducing the time interval between the steps transmitting reference clock signal and transmitting the test enable signal, by starting the functional self-test based on the phase lock time of the individual LSI under test to thereby improve the throughput of the functional self-test of the LSI.
The present invention provides a LSI including a PLL circuit for receiving a reference clock signal to generate a system clock signal, the PLL circuit comparing a phase of the system clock signal against a phase of the reference clock signal to detect a phase lock therebetween, a logic circuit for operating with the system clock signal for signal processing, and a built-in self-test (BIST) circuit for responding to a test enable signal to test the logic circuit in a functional self-test and receive test result data from the logic circuit, wherein the PLL circuit responds to a test instruction signal to generate the system clock signal and transmits the test enable signal to the BIST circuit upon detecting the phase lock under the presence of the test instruction signal.
In accordance with the LSI of the present invention, since the test enable signal is generated in the PLL circuit instead of the IC tester under the presence of the test instruction signal, the BIST circuit can starts for the functional self-test without a waiting time, whereby the throughput of the functional self-test can be improved.
The above and other objects, features and advantages of the present invention will be more apparent from the following description, referring to the accompanying drawings.